A technique is known for reducing power consumption by optimization by compiling (called as compiler optimization). For example, according to a related technique, an analysis device detects an operation resource which will not operate in an instruction section of a predetermined length when a microprocessor is in operation, and creates power control direction data. Then, with reference to the power control direction data, an adder device adds information for power control to: an instruction sequence which causes the microprocessor to operate; or a machine language instruction sequence created by translating the instruction sequence into the machine language. However, the related technique is based on the assumption that there is a state where an operation resource is not in operation in an instruction section of a predetermined length, and does not reduce power consumption in the case where such a state does not occur.
According to another related technique, power consumption is reduced as follows. A compiler of a very long instruction word (VLIW) type processor includes an interface configured to receive input of a power control compile option that gives a direction to change an arithmetic unit used in each slot and performs optimization according to a directed change of the arithmetic unit. The related technique is also based on the assumption that there is a state where the arithmetic unit is not in operation for a predetermined period of time.
For example, as examples of related art, Japanese Laid-open Patent Publication Nos. 2003-296123 and 2011-164758 are known.